The ratio of memory accesses that cause an upgrade (see general description of upgrades and other coherence related concepts in Section 3.7, “Multithreading and Cache Coherence”.)

If two threads, having their own private caches, alternatingly update a piece of shared memory, the corresponding cache lines will repeatedly change ownership and their state in the caches will also change. Specifically, when a thread writes to a cache line that was owned by a different cache, the cost of a cache line upgrade is imposed on the thread performing the write operation. This is expensive, well in parity with the cost of a cache miss.