| 8.1. Utilization Issues | ||
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 | Chapter 8. Issue Reference |  |
| 8.1. Utilization Issues | ||
|---|---|---|
| | Chapter 8. Issue Reference | |
Freja can identify three different utilization issues. Fetch and write-back utilization, which apply to the communication with memory or higher level caches that are local to the current thread. The communication utilization issue applies to communication between threads that are mapped to different caches.
Utilization issues can have a number of causes:
There may be structures with unused fields, see Section 5.1.1, “Partially Used Structures”.
There may be padding inserted into structures or between elements in an array to ensure data alignment, see Section 5.1.3, “Alignment Problems”.
There may be housekeeping data from the dynamic memory allocation between data objects, see Section 5.1.4, “Dynamic Memory Allocation”.
It may be caused by irregular access patterns, see Section 5.2.2, “Random Access Pattern”.
It may be caused by iterating over a multidimensional array in an inefficient direction, see Section 5.2.1, “Inefficient Loop Nesting”.
It may be caused by several threads accessing a common data set, partitioning the data set in an inappropriate way.
A fetch utilization issue indicates that a part of the application exhibits poor spatial locality, that is, cache lines are only partially read. The unused parts are still loaded into the cache, which means that memory bandwidth and cache space that could be used for useful data is wasted.
The fetch utilization issues has these sections:
A write-back utilization issue indicates that a part of the application has poor write-back utilization, that is, cache lines are only partially updated (written) by the application. The parts that were not updated will still be written back to memory, which results in wasted bandwidth.
The write-back utilization issues has these sections:
A communication utilization issue is reported when Freja finds two locations in different threads, or rather in two threads mapped to different caches, that communicate by reading and writing the same cache lines, but only use a small part of the cache lines in each communication cycle. By utilization a larger part of the cache lines for communication the amount of coherence misses in these locations could be reduced. See Section 5.4.2, “Poor Communication Utilization” for more information about the problem.
The communication utilization issue has these sections:
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| Chapter 8. Issue Reference |  | 8.2. Inefficient Loop Nesting |
