Conference Program


At a glance:

Monday 10 Tuesday 11 Wednesday 12 Thursday 13 Friday 14
07:30 – 08:00 Registration and Breakfast Registration and Breakfast Registration and Breakfast Registration and Breakfast Registration and Breakfast
08:00 – 08:30
08:30 – 09:00 Workshops & Tutorials Workshops & Tutorials Opening Remarks Keynote 2 Keynote 3
09:00 – 09:30 Keynote 1
09:30 – 10:00 Break Break
10:00 – 10:30 Break Break Break Session 4 &
Session 5		 Session 10
10:30 – 11:00 Workshops & Tutorials Workshops & Tutorials Session 1
11:00 – 11:30
11:30 – 12:00
12:00 – 12:30 Lunch Lunch Lunch Lunch Lunch
12:30 – 13:00
13:00 – 13:30
13:30 – 14:00 Workshops & Tutorials Workshops & Tutorials Session 2 Session 6 &
Session 7		 Session 11
14:00 – 14:30
14:30 – 15:00
15:00 – 15:30 Break Break Break Break
15:30 – 16:00 Workshops & Tutorials Workshops & Tutorials Break Session 8 &
Session 9		 Session 12
16:00 – 16:30 Session 3
16:30 – 17:00
17:00 – 17:30 Break
17:30 – 18:00 Bus to dinner (17:45) Conference Closes
18:00 – 18:30 Shuttle to Reception (Goodbye!)
18:30 – 19:00 Welcome Reception and Poster Session
(18:30 - 21:00)		 Conference Dinner
(18:30 - 22:00)
19:00 – 19:30
19:30 – 20:00
20:00 – 20:30
20:30 – 21:00
21:00 – 21:30 Shuttle to Hotel
21:30 – 22:00
22:00 – 22:30 Return to Hotel


Detailed Program

Sunday, June 9th

Note: All Sunday events will be held at the Eugene Hilton.

17:00 − 20:30 Registration
West Conference Center Lobby

Monday, June 10th

Note: All Monday events will be held at the Eugene Hilton.

07:30 − 08:30 Registration, Breakfast
West Conference Center Lobby, Wilder/Hansberry
08:30 − 10:00
1
W1: International Workshop on Runtime and Operating Systems for Supercomputers (ROSS)
Bloch
T3: It's Elemental
Sousa
10:00 − 10:30 Coffee Break
Wilder/Hansberry
10:30 − 12:00
2
W1: International Workshop on Runtime and Operating Systems for Supercomputers (ROSS)
Bloch
T3: It's Elemental
Sousa
12:00 − 13:30 Lunch
13:30 − 15:00
3
W1: International Workshop on Runtime and Operating Systems for Supercomputers (ROSS)
Bloch
T2: Fault-tolerance Techniques for HPC
Sousa
T4: DLA on Multicore with Accelerators
15:00 − 15:30 Coffee Break
Wilder/Hansberry
15:30 − 17:00
4
W1: International Workshop on Runtime and Operating Systems for Supercomputers (ROSS)
Bloch
T2: Fault-tolerance Techniques for HPC
Sousa
T4: DLA on Multicore with Accelerators
Joplin / Seeger

Tuesday, June 11th

Note: All Tuesday events will be held at the Eugene Hilton.

07:30 − 08:30 Registration, Breakfast
West Conference Center Lobby, Wilder/Hansberry
08:30 − 10:00
5
T5: PerfExpert and MACPO
Sousa
T1: Compiler Optimization
Joplin
T6: SnuCL
Seeger
10:00 − 10:30 Coffee Break
Wilder/Hansberry
10:30 − 12:00
6
T5: PerfExpert and MACPO
Sousa
T1: Compiler Optimization
Joplin
T6: SnuCL
Seeger
12:00 − 13:30 Lunch
13:30 − 15:00
7
W3: Algorithmic and Application Error Resilience (AER)
Bloch
T5: PerfExpert and MACPO
Sousa
T7: Advanced MPI
Joplin
T8: Charm++
Seeger
15:00 − 15:30 Coffee Break
Wilder/Hansberry
15:30 − 17:00
8
W3: Algorithmic and Application Error Resilience (AER)
Bloch
T5: PerfExpert and MACPO
Sousa
T7: Advanced MPI
Joplin
T8: Charm++
Seeger

Wednesday, June 12th

Note: Except for the Welcome Reception / Poster Session, all Wednesday events will be held at the Eugene Hilton.

07:30 − 08:30
Registration Open, Breakfast
West Conference Center Lobby, Wilder/Hansberry
08:30 − 09:00
Opening Remarks
O'Neill / Williams
09:00 − 10:00 Keynote Address 1
O'Neill / Williams
Session Chair: Sam Midkiff
Bob Blainey, IBM Fellow Business Meets Supercomputing
10:00 − 10:30 Coffee Break
Wilder/Hansberry
10:30 − 12:00
1
:
DSLs and Semantic Based Compilation 1
O'Neill / Williams
Chair: Boyana Norris
Andrew Stone and Michelle Strout Abstractions to Separate Concerns in Semi-Regular Grids
Thomas Henretty, Richard Veras, Franz Franchetti, Louis-Noel Pouchet, J. Ramanujam and P. Sadayappan A Stencil Compiler for Short-Vector SIMD Architectures
Chenyang Liu, Hasan Jamal, Milind Kulkarni, Arun Prakash and Vijay Pai Exploiting Domain Knowledge to Optimize Parallel Computational Mechanics Codes
12:00 − 13:30
Lunch
13:30 − 15:30
2
:
Tools and Performance Debugging
O'Neill / Williams
Chair: Sameer Shende
Jose-Maria Arnau, Joan-Manuel Parcerisa and Polychronis Xekalakis TEAPOT: A Toolset for Evaluating Performance' Power and Image Quality on Mobile Graphics Systems
Chang-Seo Park, Koushik Sen and Costin Iancu Scaling Data Race Detection for Partitioned Global Address Space Programs
Xing Wu and Frank Mueller Elastic and Scalable Tracing and Accurate Replay of Non-Deterministic Events
Xu Liu, John Mellor-Crummey and Mike Fagan A New Approach for Performance Analysis of OpenMP Programs
15:30 − 16:00 Coffee Break
Wilder/Hansberry
16:00 − 18:00
3
:
Memory and Storage
,
O'Neill / Williams
Chair: Torsten Hoefler
Kun Fang and Zhichun Zhu Conservative Row Activation to Improve Memory Power Efficiency
Sangyeun Cho, Chanik Park, Hyunok Oh, Sungchan Kim, Youngmin Yi and Greg Ganger Active Disk Meets Flash: A Case for Intelligent SSDs
Myoungsoo Jung, John Shalf and Mahmut Kandemir Design of a Large-Scale Storage-Class RRAM System
Juyoung Jung and Sangyeun Cho Memorage: Emerging Persistent RAM based Malleable Main Memory and Storage Architecture
18:00 − 18:30 Shuttle to Poster Reception
18:30 − 21:00 Welcome Reception and Poster Session with drinks, appetizers, hors d'oeuvres
The Reception will be held at the University of Oregon Schnitzer Art Museum.
20:00 − 20:15 Shuttle to Eugene Hilton

Thursday, June 13th

Note: Except for the Conference Dinner, all Thursday events will be held at the Eugene Hilton.

07:30 − 08:30
Registration Open, Breakfast
West Conference Center Lobby, Wilder/Hansberry
08:30 − 09:30 Keynote Address 2
O'Neill / Williams
Session Chair: Mario Nemirovsky
Steve Teig, President and CTO, Tabula Title: Function, Latency, Bandwidth, Power: Towards A Better Computer
09:30 − 10:00 Coffee Break
Wilder/Hansberry
10:00 − 12:00
4 (Parallel Sessions)
:
Communication and Heterogeneous Systems
O'Neill
Chair: Costin Iancu
Michail Alvanos, Ettore Tiotto, Montse Farreras, Jose Nelson Amaral and Xavier Martorell Improving Communication in PGAS Environments: Static and Dynamic Coalescing in UPC
Bogdan Prisacari, German Rodriguez, Cyriel Minkenberg and Torsten Hoefler Bandwidth-optimal alltoall exchanges in fat tree networks
Klaus Kofler, Ivan Grasso: Biagio Cosenza and Thomas Fahringer An Automatic Input-Sensitive Approach for Heterogeneous Task Partitioning
Ivan Grasso, Simone Pellegrini, Biagio Cosenza and Thomas Fahringer libWater: Heterogeneous Distributed Computing Made Easy
 
5 (Parallel Sessions)
:
Architecture 1
Williams
Chair: Valentin Puente Varona
Tapasya Patki, David Lowenthal, Barry Rountree, Martin Schulz and Bronis de Supinski Exploring Hardware Overprovisioning in Power-Constrained High Performance Computing
Mark Stephenson, Ram Rajamony and Evan Speight The Power 775 Architecture at Scale
Ruisheng Wang, Lizhong Chen and Timothy Pinkston Bubble Coloring: Avoiding Routing- and Protocol-induced Deadlocks With Minimal Virtual Channel Requirement
Keith Underwood, Eric Borch, John Sizer, Timothy Stremcha and Michael Strom Evaluating On-Die Interconnects for a 4 TB/s Router
12:00 − 13:30
Lunch
 
SRC Poster Mini Presentations
Chair: Hank Childs and Boyana Norris
13:30 − 15:00
6 (Parallel Sessions)
:
Algorithms
O'Neill
Chair: Sathish Vadhiyar
Matthew Badin, Paolo D'Alberto, Lubomir Bic, Michael Dillencourt and Alex Nicolau Improving Numerical Accuracy for Non-Negative Matrix Multiplication on GPUs using Recursive Algorithms
Azzam Haidar, Mark Gates, Stan Tomov and Jack Dongarra Toward a scalable multi-GPU eigensolver via compute-intensive kernels and efficient communication
Panagiotis Foteinos and Nikos Chrisochoides High Quality Real-Time Image-to-Mesh Conversion for Finite Element Simulations
 
7 (Parallel Sessions)
:
Architecture 2
Williams
Chair: Gabriel Marin
Komal Jothi and Haitham Akkary Tuning the Continual Flow Pipeline Architecture
Konstantinos Koukos, David Black-Schaffer, Vasileios Spiliopoulos and Stefanos Kaxiras Towards more efficient execution: A decoupled access-execute approach
Souad Koliai, Zakaria Bendifallah, Mathieu Tribalat, Cédric Valensi, Jean-Thomas Acquaviva and William Jalby Quantifying Performance Bottleneck Cost Through Differential Analysis
15:00 − 15:30 Coffee Break
Wilder/Hansberry
15:30 − 17:00
8 (Parallel Sessions)
:
Irregular Algorithms
,
O'Neill
Chair: Jim Dehnert
Xing Liu, Mikhail Smelyanskiy, Edmond Chow and Pradeep Dubey Efficient Sparse Matrix-Vector Multiplication on x86-based Many-core Processors
Nick Edmonds, Jeremiah Willcock and Andrew Lumsdaine Expressing Graph Algorithms Using Generalized Active Messages
Hari Sundar, Dhairya Malhotra and George Biros HykSort: a new variant of hypercube quicksort on distributed memory architectures
 
9 (Parallel Sessions)
:
Memory
,
Williams
Chair: Myoungsoo Jung
Gabriel Marin, Collin McCurdy and Jeffrey Vetter Diagnosis and Optimization of Application Prefetching Performance
Changhui Lin, Vijay Nagarajan and Rajiv Gupta Address-aware Fences
Vassilis Papaefstathiou, Manolis Katevenis, Dimitrios Nikolopoulos and Dionisios Pnevmatikatos Prefetching and Cache Management using Task Lifetimes
17:00 − 17:45 Break
17:45 − 18:30 Drive to Conference Dinner
Buses leaves from Eugene Hilton
18:30 − 22:00 Conference Dinner
King Estate Winery
22:00 − 22:30 Buses return to Eugene Hilton

Friday, June 14th

Note: All Friday events will be held at the Eugene Hilton.

07:30 − 08:30
Registration Open, Breakfast
West Conference Center Lobby, Wilder/Hansberry
08:30 − 09:30 Keynote Address 3
O'Neill / Williams
Session Chair: Allen Malony
James (Jim) Smith, Emeritus Professor, Department of Electrical and Computer Engineering, University of Wisconsin, Madison The Role Of Computer Designers In Reverse-Engineering The Brain
09:30 − 10:00 Coffee Break
Wilder/Hansberry
10:00 − 12:00
10
:
Runtime Techniques
O'Neill / Williams
Chair: Erik van Hensbergen
Vasudevan Rengasamy, Sathish Vadhiyar and Laxmikant V. Kale G-Charm: An Adaptive Runtime System for Message-Driven Parallel Applications on Hybrid Systems
Srinath Sridharan, Gagan Gupta and Gurindar Sohi Holistic Run-time Parallelism Management for Time- and Energy-Efficiency
Javier Bueno, Xavier Martorell, Rosa M. Badia, Eduard Ayguadé and Jesús Labarta Implementing OmpSs support for regions of data in architectures with multiple address spaces
Michael O. Lam, Jeffrey K. Hollingsworth, Bronis R. de Supinksi and Matthew P. Legendre Automatically Adapting Programs for Mixed-Precision Floating-Point Computation
12:00 − 13:30
Lunch
13:30 − 15:00
11
:
Order in the House
O'Neill / Williams
Chair: Catalin Clobanu
Pablo Prieto, Valentin Puente and Jose Angel Gregorio CMP Off-chip Bandwidth Scheduling Guided by Instruction Criticality
Wolfgang Frings, Dong H. Ahn, Matthew P. Legendre, Todd Gamblin, Bronis R. de Supinski and Felix Wolf Massively Parallel Loading
Khaled Hamidouche, Sreeram Potluri, Hari Subramoni, Krishna Kandalla and Dhabaleswar Panda MIC-RO: Enabling Efficient Remote Offload on Heterogeneous Many Integrated Core (MIC) Clusters with InfiniBand
15:00 − 15:30 Coffee Break
Wilder/Hansberry
15:30 − 17:30
12
:
GPUs
O'Neill / Williams
Chair: Rudolf Eigenmann
Xin Huo, Sriram Krishnamoorthy and Gagan Agrawal Efficient Scheduling of Recursive Control Flow on GPUs
Nabeel Alsaber and Milind Kulkarni SemCache: Semantics-aware Caching for Efficient GPU Offloading
Ping Xiang, Yi Yang, Mike Mantor, Norm Rubin, Lisa R. Hsu and Huiyang Zhou Exploiting Uniform Vector Instructions for GPGPU Performance: Energy Efficiency and Opportunistic Reliability Enhancement
Amit Sabne, Putt Sakdhnagool and Rudolf Eigenmann Scaling Large-Data Computations on Multi-GPU Accelerators
17:30 − 17:45 Conference Closes
O'Neill / Williams
17:45 Goodbye!